A semiconductor memory is composed of data storage cells arranged in rows and columns. At the time of reading from or writing into a memory, a set of external control signals and clocks are activated. The memory cells from which the data is to be read/written are accessed and then the data is read (or written) by the read (or write) circuitry. The read circuitry performs the reading operation by sensing the voltage difference developed across the bit lines (or data lines).
To ensure that desired data is read correctly, the read operation at the sense amplifier should be triggered only when sufficient voltage differential has been developed across the bit lines. This is done by ensuring a time delay between accessing a memory cell and triggering the amplifier. This time delay is also known as the memory cell discharge time. The circuitry providing this delay is called the self-timing circuitry. The self-timing circuitry should provide delay, which ensures correct reading of the memory cells. This circuitry generates a RESET signal, which produces the sense amplifier enable signal to enable the sense amplifier to sample the voltage difference across the corresponding bit lines.
In a self-timed memory array, the timing delay of a RESET signal is matched to the timing delay of the bit lines of the memory array by deriving the timing of RESET signal from a group of cells called reference cells. These reference cells have a structure identical to that of normal memory cells, and as a result, the delay in generation of the sense amplifier enable signal matches the timing delay of the bit lines.
Self-timing circuitry has now become an integral part of almost all memories designed these days. However, in certain situations a need arises for delays in a memory that can be controlled externally. This is achieved by incorporating programmable delay circuitry within a memory device. The use of programmable delay circuitry provides flexibility in selecting among multiple delay intervals depending upon circuit operation conditions or other requirements.
Programmable delay code circuitry is useful during testing of a memory at speeds different from the normal one. At the time of testing, if a device fails to perform at high operation speed, it must be tested at a slower operational speed. This is done by delaying the trigger to the sense amplifier using the programmable delay code circuitry. Programmable delay circuitry may also be used during the actual implementation of a memory device to improve the performance or yield of the device.
Different configurations of programmable delay circuitry have been used in integrated circuits till date. In one of the configurations presently used (as disclosed by U.S. Pat. No. 6,034,548 issued to Churcher et al.), the programmable delay circuit includes a signal path, a delay circuit having a plurality of delay values, a switching circuit connected to the signal path and the delay circuit for switching a selected delay value into the signal path, and a memory programmable after fabrication of the integrated circuit for storage of data which controls the switching circuit and hence the delay value switched into the signal path. The programmable memory in the integrated circuit is programmed with a code known as a delay code. This delay code represents the delay interval to be selected out of different possible delay intervals. Depending upon the delay code, a delay value is switched into the signal path.
In another configuration (as disclosed by U.S. Pat. No. 6,885,610 B2 issued to Takayanagi) a number of delayed versions of a signal are generated by a plurality of delay circuits. A programmable multiplexer or selector circuit selects among available delay options. The selector circuit is controlled by values stored in a control register, which are in turn controlled by test control signals presented to the programmable delay circuit. Thus, the delay introduced in a signal can be altered by altering the test control signals
Although, the above-mentioned techniques provide an efficient means of programming delays in an integrated circuit, however, both these methods require a extra devices in the circuitry. As a result, extra hardware is needed especially when the delay spectrum required is large.
Moreover, the circuitry used in the prior art provides a delay, which is a function of logic spice characteristics only. However, in general, the memory cell spice may be different from the spice of the periphery logic devices. As a result, there may be a differential shift in the spice characteristics of these two models. Hence a delay provided by pure logic devices may not be sufficient when there are changes in memory cell spice characteristics.
Also, any significant change in the extractions of parasitic capacitances of the bit lines results in a change in the voltage differential that gets developed across them. The delay introduced by the programming delays, however, is not affected by a change in the extractions of parasitic capacitances of the bit lines.
Also, the above mention techniques provide the same delay for a memory with a smaller number of rows as well as for a larger number of rows. However, in general, a cut with a larger number of rows needs a larger delay than that one with a smaller number of rows to generate the same voltage differential, which is sufficient for a correct evaluation by the sense amplifier. The techniques disclosed by the prior art provide a fixed delay sufficient for cuts with all row combinations. This results in performance deterioration.
Therefore, there arises a need for delay introducing circuitry, which uses less hardware and provides delays that are a function of memory cell spice characteristics and core parasitic capacitances. Also, the delay should be dependent on the size of the memory.